Copy and paste is a design error
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You're replying to a comment by Rhomboid.
On modern Intel parts, 32 bit integer division for Nehalem and Westmere is specified with a throughput of 5-13 cycles, and for Sandy Bridge it's specified with a throughput of 11-17 cycles. At 3 GHz, that's in the neighborhood of 3-4ns, which is damn impressive. In the height of the Netburst era (~2004), 32 bit integer division on Prescott was specified with a latency of 30 cycles, or around 11ns at 2.66 GHz. And if you go back to the original Pentium, it was specified as 46 cycles, which at 166 MHz is 277ns.
I guess what I'm saying is that division used to be a scary boogeyman, but it's not anymore. The hardware people have done their job.
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